Project Objectives
Europe’s future prosperity depends on its ability to design and manufacture advanced microelectronics at home. From electric vehicles and renewable energy to automation, robotics, and next-generation communication systems, semiconductor devices are at the heart of the technologies that shape our lives. Yet today, Europe accounts for only a small share of the world’s manufacturing and packaging capacity, relying heavily on overseas supply. This dependency poses a risk to strategic industries such as mobility, energy, and industrial automation—sectors that demand electronic systems of exceptional quality, reliability, and resilience, often operating for years in harsh conditions.
The E2PACKMAN project addresses this challenge by uniting leading companies, research institutions, and SMEs to strengthen Europe’s capabilities in advanced assembly and packaging. By accelerating innovation in materials, processes, and equipment, and by fostering heterogeneous integration across computing, sensing, and power devices, the project aims to close the capacity gap, secure sovereignty, and create sustainable, high-skill jobs. With a coherent approach covering the entire value chain—from chip to package to board—E2PACKMAN is set to enable the next generation of European-made electronic systems that are robust, reliable, and globally competitive.
Objective 1
Chip integration contributes to miniaturization. In WP1 we will identify the technology bricks required for going beyond the SotA in power chip integration. E.g. replacing long and tall wire loops between chips by flat Cu clips can contribute to miniaturization while also improving performance.
Objective 2
Improvement by Modelling and simulation (shorter design time, virtual prototyping introduction). This objective links to our tasks in WP2 where the design choices are based on achieving improved reliability. The design choices are based on data coming from advanced model and simulation results (KPI1).
Objective 3
Performance improvement (integrated passive). This objective is addressed in WP3, where we investigate experimentally new interconnect technology and materials suitable for high Tj operating conditions and high-power density (KPI2,KPI3).
Objective 4
Demonstrated Reliability capability for AEC-Q100. Obj. 4 is achieved in WP6 where lifetime testing and power cycling is performed according to industry standard AEC protocols. The outcome will demonstrate the reliability of the technology demonstrators (KPI4).
Objective 5
Green design and sustainability (nano-sintering). In WP3 and WP6 we focus on advanced sintering technology, sintering materials, and lifetime tests of the new technology. Since this replaces the current SotA which is Pb-solder and or wire bonds with more sustainable materials and longer lifetimes technology we aim to achieve Obj 5 within the WP3 and WP6.